It is common for serial data links to be constructed from subsidiary data streams at a lower rate. This so-called time division multiplexing requires a method for de-multiplexing data at the receiver which in turn requires timing information. For binary data transmission, this clock recovery operation is commonly done at the serial data frequency of the transmission system, e.g., the recovered clock frequency matches the serial transmission rate. These operations are currently done using nonlinear circuit elements and phase-locked-loop (PLL) techniques, or high-Q filters, as described in A. Buchwald, K. Martin, "Integrated Fiber-Optic Receivers," Kluwer, 1995, ISBN0-7923-9549-2 and "Monolithic phase locked loops and clock recovery circuits," Behzad Razavi (ed.) IEEE press, 1996, the disclosures of which are incorporated herein by reference. Such methods are complex and require high speed circuitry.
Therefore, it would be highly desirable to provide methods and apparatus for providing clock-enriched data coding at a transmitter end of a data transmission system and sub-harmonic de-multiplexing at a receiver end of the system in order to overcome the shortcomings of the prior art, as mentioned above and which otherwise exist in the art.